Y. Shih, E. Lai, J. Hsieh, T. Hsu, M.D. Wu, C. Lu, K. Ni, T.Y. Chou, L.W. Yang, K. Hsieh, M. Liaw, W.P. Lu, K.C. Chen, J. Ku, F. Ni, R. Liu, Chih-Yuan Lu
{"title":"Highly Scalable and Reliable Multi-bit/cell Nitride Trapping Nonvolatile Memory Using Enhanced ANS-ONO Process with A Nitridized Interface","authors":"Y. Shih, E. Lai, J. Hsieh, T. Hsu, M.D. Wu, C. Lu, K. Ni, T.Y. Chou, L.W. Yang, K. Hsieh, M. Liaw, W.P. Lu, K.C. Chen, J. Ku, F. Ni, R. Liu, Chih-Yuan Lu","doi":"10.1109/IEDM.2006.346824","DOIUrl":null,"url":null,"abstract":"Multi-bit/cell nitride trapping NVM (Eitan et al., 2000 and 2005) using BTBT-HH erase suffers an \"apparent\" VT loss due to interface trap (NIT) generation. The array-nitride-sealing (ANS) ONO process (Shih et al., 2005) eliminates this VT loss by blocking hydrogen from the interface. In this work we further outfit the ANS-ONO process with a nitridized Si/SiO2 interface. By introducing a rapid thermal nitridation (RTN) after a low-energy buried diffusion (BD) implantation, the new process provides not only more immunity to HH-induced NIT generation but also a path to scale the BD. A 256Mb testing chip is successfully fabricated by the new approach with excellent natural good yield (>80%) and reliability. Our new process integration shows excellent reliability, scalability, and manufacturability for multi-bit/cell nitride trapping memory","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"87 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2006.346824","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
Multi-bit/cell nitride trapping NVM (Eitan et al., 2000 and 2005) using BTBT-HH erase suffers an "apparent" VT loss due to interface trap (NIT) generation. The array-nitride-sealing (ANS) ONO process (Shih et al., 2005) eliminates this VT loss by blocking hydrogen from the interface. In this work we further outfit the ANS-ONO process with a nitridized Si/SiO2 interface. By introducing a rapid thermal nitridation (RTN) after a low-energy buried diffusion (BD) implantation, the new process provides not only more immunity to HH-induced NIT generation but also a path to scale the BD. A 256Mb testing chip is successfully fabricated by the new approach with excellent natural good yield (>80%) and reliability. Our new process integration shows excellent reliability, scalability, and manufacturability for multi-bit/cell nitride trapping memory
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