Source/drain resistance modeling in bulk and ultra-thin body SOI MOSFETs

Abstract

In this paper, the optimization of the S/D extrinsic resistance for the recessed and elevated S/D silicide contact structure through physical compact modeling and 2-dimensional TCAD simulation are investigated. A new simplified physical compact modeling is developed and applied to 90-nm SOI CMOS technology to investigate the sub-resistance component contribution and parameter sensitivity. The model-based guideline for the optimum location of silicide/Si interface in elevated S/D structure is proposed with respect to the device parameters including contact size and SOI thickness.