{"title":"Versatile analogue motion estimator architecture","authors":"M. Panovic, A. Demosthenous","doi":"10.1109/ISPA.2003.1296423","DOIUrl":null,"url":null,"abstract":"A motion estimator architecture based on analogue subsystems is presented which meets the requirements of several different video coding standards. The proposed architecture allows motion estimation parameters to be changed to meet various video standards without redesigning the hardware. Moreover, it offers reductions in size, power dissipation and consequently cost, over digital implementations, while maintaining the versatility of the digital approach. Simulated results indicate that the architecture is not sensitive to errors usually associated with the use of analogue circuits.","PeriodicalId":218932,"journal":{"name":"3rd International Symposium on Image and Signal Processing and Analysis, 2003. ISPA 2003. Proceedings of the","volume":"92 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"3rd International Symposium on Image and Signal Processing and Analysis, 2003. ISPA 2003. Proceedings of the","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPA.2003.1296423","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A motion estimator architecture based on analogue subsystems is presented which meets the requirements of several different video coding standards. The proposed architecture allows motion estimation parameters to be changed to meet various video standards without redesigning the hardware. Moreover, it offers reductions in size, power dissipation and consequently cost, over digital implementations, while maintaining the versatility of the digital approach. Simulated results indicate that the architecture is not sensitive to errors usually associated with the use of analogue circuits.