2.3 A 130-to-180GHz 0.0035mm2 SPDT switch with 3.3dB loss and 23.7dB isolation in 65nm bulk CMOS

Abstract

Single-pole double-throw (SPDT) switches are a key building block for enabling transceiver time-division duplexing (TDD) when operated as a T/R switch or for eliminating imager fluctuations when operated as a Dicke switch. To provide acceptable compromises of IMF, Pout and sensitivity in transceivers or imagers, the switches are required to feature an insertion loss of ~3dB and an isolation of ~20dB. Recently, mm-Wave/sub-mm-Wave transceiver and imager integrated circuits have gradually migrated to silicon platforms for low-cost consumer markets [1,2]. However, the associated SPDT switches operating beyond 110GHz are developed using advanced SOI or SiGe HBT technologies [3,4] and rarely implemented in CMOS due to the lossy substrate and poor transistor characteristics [2,5].