A Novel Calibration Algorithm for Timing Mismatch in Time-Interleaved ADCs

Abstract

Timing skews often generate undesirable spurs in time-interleaved ADCs (TIADC) and degrade the systems' performance seriously. In this paper, an efficient background timing skew calibration algorithm is proposed to minimize its effects. The proposed Algorithm detects the sampling-time mismatches between sub-ADCs by estimating the skew-related errors with a reference channel and aligns the sampling edge of each sub-ADC to that of the reference channel by analog variable-delay lines in the negative feedback loop. Compared with conventional background calibration methods based on complex algorithms or serious input restrictions, the proposed technique detects timing skews by only negligible hardware consisting of simple digital blocks and is applicable for a wide range of input including completely random signals. The detailed theoretical analysis and sufficient simulated results revealed that this calibration algorithm can greatly attenuate skew-related spurs and improve the property of the TIADC system significantly. What's more, it's not sensitive to some non-ideal components in actual circuits like mismatches between channels or jitters in clock circuits, which verifies the practicability and robustness of this method.