IC yield modeling and statistical circuit simulation

Abstract

An important concern whether designing a new process or maintaining an existing one is the cost of production and hence the chip yield. In order to maximize chip yield, the most significant process parameters need to be identified so that variations in these critical parameters can be minimized resulting in the highest possible chip yield. Presented in this paper is a software-based methodology for facilitating the identification of critical process parameters and relating them to circuit level performances using statistical analysis techniques and conventional simulators.