{"title":"A joint time synchronization concept for wireless communication system","authors":"H. Setiawan, M. Kurosaki, H. Ochi","doi":"10.1109/ICAICTA.2014.7005950","DOIUrl":null,"url":null,"abstract":"This paper presents a concept of common timing detection for three different wireless communication standards i.e. WLAN, WiMAX and LTE. We propose a system consists of sample rate conversion, symmetry-based auto-correlation, and peak detector. The correlation part consists of a single 256-tap symmetric-based auto-correlation circuit and a peak detector with an adaptive threshold value. The fixed point simulation results show that the proposed system has satisfied the minimum receiver sensitivity requirements that specified by the standards. Moreover, the proposed system has fitted for FPGA Virtex-5 XC5VTX240T implementation by utilizing 50 percent of total look up table (LUT) in the FPGA, and can reach the clock frequency up to 76.7MHz.","PeriodicalId":173600,"journal":{"name":"2014 International Conference of Advanced Informatics: Concept, Theory and Application (ICAICTA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference of Advanced Informatics: Concept, Theory and Application (ICAICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAICTA.2014.7005950","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a concept of common timing detection for three different wireless communication standards i.e. WLAN, WiMAX and LTE. We propose a system consists of sample rate conversion, symmetry-based auto-correlation, and peak detector. The correlation part consists of a single 256-tap symmetric-based auto-correlation circuit and a peak detector with an adaptive threshold value. The fixed point simulation results show that the proposed system has satisfied the minimum receiver sensitivity requirements that specified by the standards. Moreover, the proposed system has fitted for FPGA Virtex-5 XC5VTX240T implementation by utilizing 50 percent of total look up table (LUT) in the FPGA, and can reach the clock frequency up to 76.7MHz.