Low-Ripple CMOS Switched-Capacitor Power Converter With Closed-Loop Interleaving Regulation

Abstract

This paper presents a new integrated switched-capacitor (SC) power converter with an interleaving regulation scheme. By dividing the original power stage into sub-units and operating each sub-unit in an interleaving way, the converter achieves attractive low ripple voltage and transient performance, without compromising other design parameters. The closed-loop operation ensures accurate voltage regulation at any desired levels. The design was fabricated with 0.35 mum CMOS N-well process. The die area including all pads and power transistors is 3.52 mm2. Measurement results show that, with a supply voltage of 1.5 V and a load current of 250 mA, the output of the converter is well regulated at 2.5 V with only 9-mV ripple. The maximum efficiency of 82.3 % is achieved, when the output power reaches 625 mW