Memory access stage removal technique for dynamic power reduction in embedded CPUs

Abstract

There are several reasons why power efficiency is becoming increasingly important for portable systems powered by batteries. At the same time these systems are becoming physically smaller and battery weight is becoming more significant. Users demand longer battery life and this can only be obtained either by increasing the capacity of the battery or by increasing the efficiency of the logic. The rate of progress in battery technology is slow, so the focus is on the digital designer to improve efficiency. This paper discusses the power budget for the 32 - bit conventional processor and then suggests a technique which is implemented at design level for power optimization along with the comparison of power results for standard and the modified structures of the system. The proposed work is simulated, synthesized, tested and verified by using tools such as Xilinx ISE - 13.1, Xilinx XPower and ModelSim SE PLUS-6.5 for waveform generation and XPowerAnalyzer for power analysis.