Novel design evaluation engine for A/D converters

Abstract

Environment for testing analog-to-digital converters is presented in this article. It is a novel concept of powerful engine suitable for design and verification of generic type ADCs in Mentor Graphics IC Studio software. Source code of each block of the design is written in Verilog-A which offers relatively effortless portability on different design systems (e.g. Cadence). This approach brings to IC design engineers easy to use supportive tool. The core of our proposal is based on Servo- Loop with improved search algorithm [1]. The simulation outputs are curves of static INL and DNL. A part of article deals with the example of simple Flash ADC testing.