{"title":"Optimizations of Negative Capacitance Independent Dual-Gate FinFETs","authors":"Wenjing Bai, Jianping Hu, Tingfeng Yang","doi":"10.1109/NANO.2018.8626333","DOIUrl":null,"url":null,"abstract":"In this paper, we introduce a novel negative-capacitance device, named as negative-capacitance independent dual-gate FinFETs (NC-IDG-FinFETs) that can reduce the number of transistors used in circuit designs. We stack thin ferroelectric (FE) layers into the two gate stacks of baseline traditional independent dual-gate FinFET devices. We chose HfSiO (with the typical anisotropy constants of $\\alpha_{FE}=-8.65\\mathrm{e}10$ cm/F, $\\beta_{FE}=1.92\\mathrm{e}20$ cm5/ F/C2, and $\\gamma_{FE}=0$ cm9/F/C4) as the material with negative capacitance effect. The high-K dielectric Hf02 is used between the FE layer and the channel. We optimize the turn-on currents, leakage currents, and the switching current ratio by adjusting ferroelectric thickness. Simulation results show that the proposed devices can increase the on-state current and decrease the leakage current, and increase the switching current ratio.","PeriodicalId":425521,"journal":{"name":"2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NANO.2018.8626333","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, we introduce a novel negative-capacitance device, named as negative-capacitance independent dual-gate FinFETs (NC-IDG-FinFETs) that can reduce the number of transistors used in circuit designs. We stack thin ferroelectric (FE) layers into the two gate stacks of baseline traditional independent dual-gate FinFET devices. We chose HfSiO (with the typical anisotropy constants of $\alpha_{FE}=-8.65\mathrm{e}10$ cm/F, $\beta_{FE}=1.92\mathrm{e}20$ cm5/ F/C2, and $\gamma_{FE}=0$ cm9/F/C4) as the material with negative capacitance effect. The high-K dielectric Hf02 is used between the FE layer and the channel. We optimize the turn-on currents, leakage currents, and the switching current ratio by adjusting ferroelectric thickness. Simulation results show that the proposed devices can increase the on-state current and decrease the leakage current, and increase the switching current ratio.