{"title":"Energy-efficient continuous-time linear equalizer for short-haul optical communications","authors":"Fengdeng Li, Qingsheng Hu","doi":"10.1109/ICASID.2015.7405665","DOIUrl":null,"url":null,"abstract":"This paper presents a power estimate method to predict the energy efficiencies of continuous-time linear equalizers for short-haul optical communications. In order to forecast the energy efficiency over data rates, which is defined as power dissipation divided by the corresponding data rate, a reference circuit meeting some major features is established, whose energy efficiency functions as the start point of the scaling process. By exploring the relationship between the scaled circuits working at different data rates and the reference circuit, the energy efficiency model is obtained. With this equation-based model, the energy efficiencies of the scaled CTLEs with different boost values are estimated in both CMOS 180-nm process and 90-nm process. Simulation results are given and analyses show that the model is accurate, model results are very close to SPICE simulation results.","PeriodicalId":403184,"journal":{"name":"2015 IEEE 9th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 9th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASID.2015.7405665","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a power estimate method to predict the energy efficiencies of continuous-time linear equalizers for short-haul optical communications. In order to forecast the energy efficiency over data rates, which is defined as power dissipation divided by the corresponding data rate, a reference circuit meeting some major features is established, whose energy efficiency functions as the start point of the scaling process. By exploring the relationship between the scaled circuits working at different data rates and the reference circuit, the energy efficiency model is obtained. With this equation-based model, the energy efficiencies of the scaled CTLEs with different boost values are estimated in both CMOS 180-nm process and 90-nm process. Simulation results are given and analyses show that the model is accurate, model results are very close to SPICE simulation results.