Minimizing the effects of tolerance faults on hardware realizations of cellular neural networks

Abstract

In this paper a procedure for minimizing the effects of tolerance faults in cellular neural network (CNN) chips is presented. The simulation system SCNN was connected with the "CNN prototyping system" for adjusting the parameter values of the cp300 CNN chip. Results showing the erroneous outputs of the VLSI chip are presented, together with a suitable way for adapting parameter directly to a CNN realization.