Application Aware DRAM Bank Partitioning in CMP

Abstract

Main memory is a shared resource among cores in a chip and the speed gap between cores and main memory limits the total system performance. Thus, main memory should be effectively accessed by each core. Exploiting both parallelism and locality of main memory is the key to realize the efficient memory access. The parallelism between memory banks can hide the latency by pipelining memory accesses. The locality of memory accesses improves hit ratio of the row buffer in DRAM chips. The state-of-the-art method called bpart is proposed to improve memory access efficiency. In bpart one bank is monopolized by one thread and this monopolization improves row buffer locality because of alleviating inter-thread interference. However, bpart is not effective for the thread which has poor locality. Moreover, the bank level parallelism is not exploited. We propose the new bank partitioning method which exploits parallelism in addition to locality. Our method applies the two types of bank usage. One usage is that low locality threads share banks to improve parallelism, and the other usage is that each high locality thread monopolizes each bank to improve row buffer locality. We evaluate our proposed method by our in-house software simulator with SPEC CPU 2006 benchmark. On Average, system throughput is increased by 1.0% and minimum speedup (fairness metrics) is increased by 7.9% relative to bpart. This result shows that our porposed method has better performance and fairness than bpart.