Post-layout circuit speed-up by event elimination

Abstract

We propose a novel technique for post-layout delay optimization. This technique identifies the Boolean space corresponding to late arriving transitions at the outputs of delay-critical subcircuits within the given circuit. The transitions are eliminated from the outputs by implementing the corresponding logic separately and merging them with the original circuit through some control logic. Experimental results suggest that this technique can speed up circuits even when the circuits have already been optimized for delay to the fullest extent.