High Speed Hardware for March C¯

Abstract

The variations of March tests are extensively used for functional test of SRAMs and DRAMs. This work proposes hardware realization of March C- to enable efficient fault detection in memories. The properties of single length cycle attractor cellular automata are exploited to memorize the status (faulty/non-faulty) of memory words during read (r0/r1) operation of the March C- algorithm. It effectively reduces the overhead of comparison that is required in a conventional test structure, to take decision on the faults in memory.