A 25–28Gb/s PLL-based full-rate reference-less CDR in 0.13μm SiGe BiCMOS

Abstract

A 25–28Gb/s full-rate reference-less CDR is presented and designed in a standard 0.13μm SiGe BiCMOS process, which can be applicable to nearly all classical 100G communication protocols by multi-channel configuration. It consists mainly of a full-rate phase frequency detector, a quadrature voltage control oscillator and two voltage to current convertors with loop filters. A dual-loop topology is adopted in order for a wide frequency acquisition range and an excellent jitter performance. Simulation results show that the proposed CDR operates properly at a data rate of 25–28Gb/s. When a 25Gb/s PRBS data is applied, the jitters of the recovered clock and data are 0.34ps and 2.8ps, respectively, with 91 mA current consumption from a single power supply of 1.7V.