Hardware Scheduler Performance on the Plural Many-Core Architecture

Abstract

The Plural many-core architecture combines hundreds of simple cores, lock-free shared memory, hardware scheduler and a task-based programming model. The hardware scheduler enables fast scheduling and allocation of fine grain tasks to all cores. Scheduler performance is evaluated based on an architectural simulator and on multiple benchmarks representing a wide variety of inherent parallelism. Several architectural alternatives and scheduler configurations are simulated. It is shown that a scheduler with capacity to schedule and terminate 10 task-instances per cycle, along with a task queue of as little as two slots near each core, is sufficient to utilize 256 cores.