VLSI Implementation of a Energy Recovery 4-2 Compressor using PBL

Abstract

Approximate computing is employed in the image processing and multimedia applications since it is less difficult and consumes less power. Compressor outputs are estimated to construct estimated compressor. The scientific literature, which suggests a variety of circuits built with approximate 4-2 compressors, has created a lot of concern in approximation of multipliers. In exact compressors previously, emerged as a feasible solution for implementing approximate multipliers. In this project, we discovered that while keeping high speeds, it further decreases the power dissipation of approximation circuits using Pulse Boost Logic Method. We constructed a 4-2 compressor circuit employing to illustrate power savings and speed capabilities, using pulse boost logic. Cadence tool is used to run simulations with 45nm technology. At 800 MHz, our results reveal that a PBL-based approximation 4-2 compressor architecture saves 64% more power than a regular CMOS-based design. We also discussed how an accurate 4-2 compressor was designed using CMOS technology, combining approximation and ER computing can save 89% of power in a 4-2 compressor. We also mentioned that the suggested approximate 4-2 compressor based on PBL consumes 65% less energy than the existing one. Approximation 4-2 compressor is based on CMOS. The suggested 4-2 compressor with pulse boost logic-based approximation has been tested for functionality.