Enhanced dqPLL Architecture based on THD Compensation Blocs used in Three-Phase Smart Grid Synchronization

Abstract

The Synchronization between the different sources, is an important task in Smart Grids application. However, the grid source is not a pure sinusoidal in the real case, and the deformation of the input signal due to the presence of harmonic frequencies caused by non-linear loads connected to the grid. There undesired frequencies are considered as a disturbance for the voltage grid, and needed to be filtrated to be able to detect the fundamental nominal frequency of the grid by the synchronization system. When disturbances occur, Power Sources necessitates appropriate control techniques in order to stay connected and contribute appropriately to overall grid stability. Furthermore, the disconnection of these sources due to synchronization problems could result a loss of energy generation. The control process is mostly dependent on synchronization algorithms, which must identify grid voltage state quickly and precisely (e.g., phase, amplitude, and frequency). Typically, Phase Locked Loop (PLL) synchronization techniques are commonly utilized for grid voltage monitoring. PLL design and performance have a direct impact on the Grid Side Converter (GSC). This paper presents an enhanced architecture of PLL used to synchronize Three-Phase Electric Power Sources under harmonically distorted grid condition. Finally, comparing to the classical architecture. MATLAB digital simulation results shows that the proposed architecture offers a 40dBm undesirable harmonics compensation and an enhancement of the three-phase signal purity from 14% to 0.01% of THD.