Thermal scaling consideration of Si MOSFETs with gate length typically larger than 100 nm

Abstract

Scaling issues in thermal behavior of silicon MOSFETs have been discussed for devices with typically larger than 100 nm. Cutting edge technologies of silicon devices are exploring the issues in deep nanometer length scales, where it is claimed that the conventional Fourier-based thermal model does not apply. It is also claimed that the BTE-based transport model is the theoretical tool to discuss the transport phenomena in sub-100 nm length scale to a certain extent of miniaturization. There however still exist unorganized thermal issues to be considered in over-100 nm regime. This research investigates the trend of thermal issues, mainly the lattice and carrier temperatures, based on the device scaling. Simple algebraic model of lattice and electron temperatures of bulk Si MOSFET is developed. Thermal behavior of the devices is discussed based on various scaling laws and actual trend. A Multi-fluid model, a full set of partial difference equations of continuum model and constitutive equations, is solved numerically to obtain the temperature distributions in the device. The results show clear threshold of the length scale where the temperature distribution and the hot spot, spatially local high temperature region, behavior changes drastically with miniaturization. Discussions show the characteristics of thermal scaling of bulk Si MOSFETs over 100 nm range.