Chwen-Cher Chang, J. Lee, Mike Stabenfeldt, R. Tsay
{"title":"A practical all-path timing-driven place and route design system","authors":"Chwen-Cher Chang, J. Lee, Mike Stabenfeldt, R. Tsay","doi":"10.1109/APCCAS.1994.514612","DOIUrl":null,"url":null,"abstract":"We have developed a practical timing-driven design system that achieves 17% cycle time improvement with only up to 32% run time penalty, and as low as 1% area overhead in real, 5000-7000-cell designs. This system is based on a Slack Graph concept that efficiently and effectively represents all-path timing constraints and allows optimal trade-off between timing and die size.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.1994.514612","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
We have developed a practical timing-driven design system that achieves 17% cycle time improvement with only up to 32% run time penalty, and as low as 1% area overhead in real, 5000-7000-cell designs. This system is based on a Slack Graph concept that efficiently and effectively represents all-path timing constraints and allows optimal trade-off between timing and die size.