Optimization of FPGA-based circuits for recursive data sorting

Abstract

The paper describes sequential and parallel methods of recursive data sorting that are applied to binary trees. Hardware circuits implementing these methods are based on the model of a hierarchical finite state machine, which provides support for recursion in hardware. It is shown that the considered technique allows the known optimization methods for conventional state machines to be applied directly. The described circuits have been implemented in commercial FPGAs and tested in numerous examples. Analysis and comparison of alternative and competitive techniques is also done in the paper.