A high resolution and low jitter linear delay line for IR-UWB template pulse synchronization

O. Z. Batur, Naci Pekcokguler, Günhan Dündar, M. Koca
{"title":"A high resolution and low jitter linear delay line for IR-UWB template pulse synchronization","authors":"O. Z. Batur, Naci Pekcokguler, Günhan Dündar, M. Koca","doi":"10.1109/ECCTD.2015.7300117","DOIUrl":null,"url":null,"abstract":"In this paper, we present a very low jitter reconfigurable shunt capacitor delay line. The delay line produces configurable linear delay for pulse synchronization of high data rate coherent template based IR-UWB receivers. The delay line is composed of coarse and fine synchronization delay stages. The delay values of 52 pS/step, 17.5 pS/step and 4.5 pS/step and their combinations are possible with 32 control steps. 5 bit up/down counters with asynchronous reset are employed to achieve minimum pin number as well as fast configuration on the delay line. The maximum frequency of the input signal is 600 MHz. Incremental control steps can be configured in less than 1 nS. Long time additive jitter is measured as 2.3 pS.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 European Conference on Circuit Theory and Design (ECCTD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2015.7300117","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

Abstract

In this paper, we present a very low jitter reconfigurable shunt capacitor delay line. The delay line produces configurable linear delay for pulse synchronization of high data rate coherent template based IR-UWB receivers. The delay line is composed of coarse and fine synchronization delay stages. The delay values of 52 pS/step, 17.5 pS/step and 4.5 pS/step and their combinations are possible with 32 control steps. 5 bit up/down counters with asynchronous reset are employed to achieve minimum pin number as well as fast configuration on the delay line. The maximum frequency of the input signal is 600 MHz. Incremental control steps can be configured in less than 1 nS. Long time additive jitter is measured as 2.3 pS.
一种用于IR-UWB模板脉冲同步的高分辨率低抖动线性延迟线
本文提出了一种低抖动可重构并联电容器延迟线。该延迟线可产生可配置的线性延迟,用于高数据速率相干模板IR-UWB接收机的脉冲同步。延迟线由粗同步延迟段和细同步延迟段组成。在32个控制步长下,可以实现52 pS/步、17.5 pS/步和4.5 pS/步的延时值及其组合。采用异步复位的5位上行/下行计数器,以实现最小引脚数以及延迟线上的快速配置。输入信号的最大频率为600mhz。增量控制步骤可以配置在小于1ns的范围内。长时间加性抖动测量为2.3 pS。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信