O. Z. Batur, Naci Pekcokguler, Günhan Dündar, M. Koca
{"title":"A high resolution and low jitter linear delay line for IR-UWB template pulse synchronization","authors":"O. Z. Batur, Naci Pekcokguler, Günhan Dündar, M. Koca","doi":"10.1109/ECCTD.2015.7300117","DOIUrl":null,"url":null,"abstract":"In this paper, we present a very low jitter reconfigurable shunt capacitor delay line. The delay line produces configurable linear delay for pulse synchronization of high data rate coherent template based IR-UWB receivers. The delay line is composed of coarse and fine synchronization delay stages. The delay values of 52 pS/step, 17.5 pS/step and 4.5 pS/step and their combinations are possible with 32 control steps. 5 bit up/down counters with asynchronous reset are employed to achieve minimum pin number as well as fast configuration on the delay line. The maximum frequency of the input signal is 600 MHz. Incremental control steps can be configured in less than 1 nS. Long time additive jitter is measured as 2.3 pS.","PeriodicalId":148014,"journal":{"name":"2015 European Conference on Circuit Theory and Design (ECCTD)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 European Conference on Circuit Theory and Design (ECCTD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2015.7300117","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
In this paper, we present a very low jitter reconfigurable shunt capacitor delay line. The delay line produces configurable linear delay for pulse synchronization of high data rate coherent template based IR-UWB receivers. The delay line is composed of coarse and fine synchronization delay stages. The delay values of 52 pS/step, 17.5 pS/step and 4.5 pS/step and their combinations are possible with 32 control steps. 5 bit up/down counters with asynchronous reset are employed to achieve minimum pin number as well as fast configuration on the delay line. The maximum frequency of the input signal is 600 MHz. Incremental control steps can be configured in less than 1 nS. Long time additive jitter is measured as 2.3 pS.