Rapid prototyping and synthesis of a self-testing ABS controller using CAD tools

Abstract

This paper reports simulation, synthesis, and eventual layout of an automotive Anti-lock Brake system (ABS) digital controller onto FPGA technology, and the potential migration of the design onto ASIC technology. Examination of its functionality, real-time response, implementation and testability is performed in an attempt to measure the usefulness of higher level design entry facilities such as VHDL in a rapid prototyping environment. Continuous online testing is included using periodic sample injections where the resultant generated values are compared to signatures known a priori, without compromising functionality. Conclusions are drawn from the design's simulation and synthesis using VHDL onto FPGAs, ASIC migration, and CAD Tool capabilities/requirements/limitations with respect to real-time, data path synthesis for general controller applications involving asynchronous elements.<>