The Study of the Device Performance of the Hetero-junction Vertical Trench MOSFET

Abstract

In this paper, a Hetero-junction Vertical Trench MOSFET (HVTFET) is proposed. The HVTFET has a multilayer structure. Compared with FinFETs and GAAs, the HVTFET provides a new method to effectively overcome the DIBL effect of the small-size IC. The channel length Lch of HVTFET is determined by the thickness of the epitaxial channel region, so the Lch can be reduced greatly, therefore the operating frequency of the HVTFET can be greatly increased. The HVTFET can achieve higher Vdd by increasing the length of the low-doped drain region or reducing its doping concentration. The 7nm HVTFET simulation model has been established by using Sentaurus TCAD and it can work normally. The HVTFET breaks though the traditional IC reduction rule, and the HVTFET will lead IC to move forward in the future.