Efficient Mapping without Deadlock on the Many-core Neural Network Chip

Abstract

Many-core neural network chip is widely developed for the deep learning. Many-core architecture brings high parallelism while makes the model-to-core mapping intractable. Previous work focus on the functionality of the entire system, whereas, the mapping quality and deadlock issues have yet to be addressed well. In this paper, we present an algorithm which automatically maps a given neural network model onto the generic many-core chip architecture. Experimental results show that the proposed algorithm is quite efficient, and significant saving of the routing time can be achieved. Specifically, compared to the baseline of zigzag mapping, our solution is able to realize deadlock-free routing with 40.9% and 30.4% routing time saving for multi-layer perceptron and convolutional neural network applications, respectively.