A systematic experimental investigation of thermal degradation mechanisms in lidded flip-chip packages: Effects of thermal aging and cyclic loading

Abstract

This research effort is geared towards establishing a robust virtual-qualification methodology for thermal performance of flip-chip packages. In the experimental analysis presented here, test vehicles were designed and tested for degradation in the module-level thermal interface material under high temperature storage (at 100C, 125C and 150C) exposure and deep thermal cycling (−40C/+125C) conditions. The experiments conducted in this study will encompass a wide range of thermo-mechanical conditions that not only explore known JEDEC variables but also provide unique insights into understanding the effects of indirect thermal degradation drivers such as package assembly loads and chip-junction temperature variations during thermal power inputs during readouts.