A 234–248 GHz power efficient fundamental VCO using 32 nm CMOS SOI technology

Abstract

A 240 GHz fundamental oscillator is demonstrated using the IBM CMOS SOI 32 nm process. The design was based on a Colpitts differential topology, where the gate capacitance of the device is used as a part of the inductor-capacitor tank for tuning. A peak output power level of 0.2 mW (-7 dBm) was achieved, while the total power consumption was 13 mW, reaching a record power efficiency of 1.5 %. A tuning bandwidth of 11 GHz was achieved by changing the gate bias level, while a total tuning range of 13.5 GHz was achieved by controlling both the gate and the drain bias. The design consumes a core area of only 50×80 μm2 and requires no buffer to drive the external 50 Ω termination.