High-level synthesis of throughput-optimized and energy-efficient approximate designs

Abstract

Approximate accelerators for throughput-demanding error-resilient kernels can be a solution to meet design requirements with acceptable deviation from the exact implementation. However, handcrafting approximate accelerators may impose prohibitive development time and cost overheads. In this scenario, approximate High-Level Synthesis (HLS) has been proposed to deal with the increased design complexity. Nevertheless, current tools are not suitable for exploring throughput optimizations, being instead constrained to perform specific improvements on area, power, and average performance. In this work, we propose the use of HLS to generate Pareto-optimal accelerators for applications facing throughput constraints. We present an approximate HLS tool able to improve the throughput of such accelerators by up to 80% with no additional area costs, while introducing manageable error for most applications.