{"title":"Design of CS-VCO with band gap reference in 0.18μm CMOS technology","authors":"V. G. Nasre, G. Asutkar","doi":"10.1109/RTEICT.2017.8256621","DOIUrl":null,"url":null,"abstract":"Presently design of a linear and wide range voltage controlled oscillator for analog and mixed mode signal applications with lesser design cycle time is a challenging work for Electronics Engineers. Band Gap reference voltage source is required, since the power supply noise is one of the important factors that affect the PLL noise performance. This paper describes the new design technique of the Band Gap Reference Current Starved Voltage Controlled Oscillator (BG-CSVCO) circuit to reduce power supply noise for PLL application. The BG-CSVCO circuit is designed and simulated using 0.18μm CMOS Technology. The BG-CSVCO has frequency range from 1.59 MHz to 2.87 GHz for the tuning range 0.2V to 1.8V and power consumption is 1.336mW. The supply voltage VDD is 1.8V.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"227 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTEICT.2017.8256621","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Presently design of a linear and wide range voltage controlled oscillator for analog and mixed mode signal applications with lesser design cycle time is a challenging work for Electronics Engineers. Band Gap reference voltage source is required, since the power supply noise is one of the important factors that affect the PLL noise performance. This paper describes the new design technique of the Band Gap Reference Current Starved Voltage Controlled Oscillator (BG-CSVCO) circuit to reduce power supply noise for PLL application. The BG-CSVCO circuit is designed and simulated using 0.18μm CMOS Technology. The BG-CSVCO has frequency range from 1.59 MHz to 2.87 GHz for the tuning range 0.2V to 1.8V and power consumption is 1.336mW. The supply voltage VDD is 1.8V.