Acceleration of scan-based on-chip delay measurement using extra latches and multiple asynchronous transfer scan chains

Abstract

This paper presents a fast scan-based on-chip delay measurement with variable clock generator using extra latches and multiple asynchronous transfer scan chains. Usual scan-based on-chip delay measurement requires continuous scan-in operation for assigning the identical test vectors and continuous scan-out operations for transferring the identical test responses, both of which result in long measurement time. By using the proposed asynchronous multiple scan chains with some extra latches, the proposed delay measurement system can reduce the measurement time considerably. the identical test responses using the proposed asynchronous multiple scan chanins as well as using the extra latches. The pulse width modification circuits are inserted to the asynchronous transfer scan path for robust asynchronous transfer. The simulation results show that the measurement time of the proposed method is 30.8 % of the conventional one under the condition that the length of scan chains is 64.