Scalable LEON 3 based SoC for multiple floating point operations

Abstract

The low Power consumption and high performance are two main directions in the development of modern microprocessor architectures used for System on Chip. In general there are two excluding branches of System on Chip evolution, where multiple Processors are on chip or multiple co-processors on the chip to improve the performance. The paper present methodology for interfacing multiple Floating Point Units with LEON3 processor IP core for low power or high performance systems. It compares performance of basic LEON3 based SoC without FPU and with multiple FPU where multiple floating point operations can be computed in parallel. The enhanced SoC is synthesized and implemented on Xilinx FPGA. The Area and power comparison is shown, The 8 FPU increase power requirement by 3 % only giving parallel speed up by 8 times.