Design of a low-cost integrated 0.25 /spl mu/m CMOS Bluetooth SOC in 16.5 mm/sup 2/ silicon area

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992953

J. Cheah, E. Kwek, E. Low, C. Quek, C. Yong, R. Enright, J. Hirbawi, A. Lee, Hongyu Xie, Long Wei, L. Luong, Jianping Pan, Shih-Tsung Yang, Walter Lau, Wai-Lim Ngai

引用次数: 4

Abstract

A complete 0.25 /spl mu/m CMOS SOC Bluetooth solution adopts a two-die in a single MCM chip packaging approach with minimum product cost as the most important design goal while maintaining competitive power consumption and RF performance.

查看原文本刊更多论文

在16.5 mm/sup / 2/硅片面积上设计一种低成本集成0.25 /spl μ m CMOS蓝牙SOC

一个完整的0.25 /spl mu/m CMOS SOC蓝牙解决方案采用单MCM芯片封装方法，以最小的产品成本为最重要的设计目标，同时保持有竞争力的功耗和射频性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

自引率

0.00%

发文量