Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations

Abstract

We have proposed the effective stencil computation method and the architecture by employing multiple small FPGAs with 2D-mech topology. In this paper, we show that our proposed architecture works correctly on the real 2D-mesh connected FPGA array. We developed a software simulator in C++, which emulates our proposed architecture, and implemented two prototype systems in Verilog HDL. One prototype system is for logic verification with communication modules and the other is for estimation of power consumption without communication modules. We run the former prototype system for 2M cycles and check the behavior with the software simulator. Our architecture is developed towards a low-power accelerator of many FPGAs. The evaluation result with the second prototype shows that the system of a single FPGA node with eight floating-point adders and eight floating-point multipliers archives 2.24GFlop/s in 0.16GHz operations with 2.37W power consumption. This performance/W value is about six-times better than NVidia GTX280 GPU card.