Design of Low Power Multiplier using CNTFET

Abstract

Multiplication is an essential vital role in arithmetic operations. In fact, multiplication is allotted on operations like Multiply and Accumulate (MAC). The exaggerate form of Braun multiplier is the Baugh-Wooley multiplier. This work proposes the design of Low-power Baugh-Wooley Multiplier with CMOS full adder with different topologies like 10T, 14T, 17T as well as with CNTFET full adders using different topologies like 10T, 14T, 17T. All circuits are designed and simulated using HSPICE Tool.