A study of insulated and passivated gate technology for InP FETs

Abstract

The effects of using a new surface passivation technique prior to PECVD SiO/sub 2/ deposition were studied, and the performance of the devices was correlated with the state of the interface at the gate electrode. Devices with gates made using the passivation only, passivation and subsequent SiO/sub 2/ deposition, and SiO/sub 2/ deposition without passivation were studied for a uniformly doped n-channel InP FET. The unpassivated SiO/sub 2/ insulated gates produced the lowest transconductance (g/sub m/) values: passivation prior to SiO/sub 2/ deposition improved the characteristics of the devices and increased g/sub m/ significantly. The passivated enhanced barrier gates produced the best characteristics and the highest transconductances consistently. In general the enhanced barrier gates demonstrated twice as high transconductance values as the SiO/sub 2/ insulated gates.<>