Direct Bonded Heterogeneous Integration (DBHi) Si Bridge

K. Sikka, R. Bonam, Yang Liu, P. Andry, Dishit P. Parekh, Aakrati Jain, M. Bergendahl, R. Divakaruni, Maryse Cournoyer, P. Gagnon, Catherine Dufort, I. de Sousa, Hongqing Zhang, Ed Cropp, T. Wassick, H. Mori, S. Kohara
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引用次数: 14

Abstract

We introduce a new packaging technology termed as Direct Bonded Heterogeneous Integration (DBHi) where a Si-bridge is directly bonded to and in between processor chips using Cu pillars, allowing high-bandwidth low-latency low-power communication between the chips. The DBHi package structure, test vehicle design, and bond and assembly details are first described. The test vehicle package consists of chips with standard interconnect pitch where they join to a laminate chip-carrier and fine-pitch pads in the region where the chips joins to a bridge. The bridge has Cu pillars correspondingly mating to the pads on the chips. The bond and assembly sequence starts with first joining the silicon chips and bridge using a thermocompression bonding process followed by a mass reflow join of the chips to the laminate. The assembly is then underfilled and capped using specialized techniques. Mechanical modeling was extensively used to simulate the DBHi structure and assembly process to allow material selection and reliability prediction. The mechanical models were calibrated using warpage measurements. The stress/strain reliability metrics of the DBHi package are compared to a non-bridge package of the same dimensions. Results show that the main focus should be directed towards ensuring a robust assembly process as the standard reliability stress/strain metrics of the DBHi package are very similar to a non-bridge package. Thermal measurements using chip heaters and temperature sensors were conducted to calibrate a numerical thermal model of the DBHi package. The thermal model was exercised to show the relation between the allowable chip and bridge power densities for the particular package size and cooling conditions. DBHi test packages were created using the best-known assembly process and then measured for continuity performance. A variety of inter- and intra-bridge daisy chain nets were incorporated into the test vehicle for continuity measurements. Post-assembly continuity measurements demonstrated a robust assembly process for multiple rounds of assembly. Reliability performance was demonstrated using standard JEDEC tests of thermal cycling, aging, and temperature/humidity.
直接键合异质集成(DBHi)硅桥
我们介绍了一种新的封装技术,称为直接键合异构集成(DBHi),其中硅桥直接键合到处理器芯片之间,并使用铜柱,允许芯片之间的高带宽,低延迟,低功耗通信。首先介绍了DBHi封装结构、测试车辆设计以及连接和装配细节。测试车辆封装由具有标准互连间距的芯片组成,这些芯片连接到层压板芯片载体,并在芯片连接到桥的区域使用细间距衬垫。电桥的铜柱与芯片上的衬垫相匹配。粘合和组装顺序首先使用热压粘合工艺连接硅芯片和桥接,然后将芯片大量回流连接到层压板上。然后使用专门的技术对组件进行欠填充和封盖。机械建模被广泛用于模拟DBHi的结构和装配过程,以允许材料选择和可靠性预测。力学模型是用翘曲量来校准的。DBHi封装的应力/应变可靠性指标与相同尺寸的非桥封装进行了比较。结果表明,由于DBHi封装的标准可靠性应力/应变指标与非桥接封装非常相似,因此应将重点放在确保稳健的装配过程上。利用芯片加热器和温度传感器进行了热测量,以校准DBHi封装的数值热模型。运用热模型计算了特定封装尺寸和冷却条件下芯片和电桥允许功率密度之间的关系。DBHi测试包是使用最著名的组装过程创建的,然后测量连续性性能。各种桥间和桥内菊花链网被纳入测试车辆进行连续性测量。装配后的连续性测量证明了多轮装配的稳健装配过程。可靠性性能通过标准JEDEC热循环、老化和温度/湿度测试进行验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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