Influence of input voltage swing on 0.18 /spl mu/m NMOS aging estimated by self-stressing testers

Abstract

Self-stressing testers are used to study the impact of input voltage swing on the aging behavior of 0.18 NMOS devices in inverters. When the frequency and rise/fall time of the input pulse are altered, we demonstrate that the effective aging time 't/sub eff/' per clock cycle varies with the rise/fall transitions and is the main factor in deciding NMOS degradation.