N. Collaert, A. De Keersgieter, A. Dixit, I. Ferain, L. Lai, D. Lenoble, A. Mercha, A. Nackaerts, B. Pawlak, R. Rooyackers, T. Schulz, K.T. Sar, N. Son, M. V. van Dal, P. Verheyen, K. von Arnim, L. Witters, De Meyer, S. Biesemans, M. Jurczak
{"title":"Multi-gate devices for the 32nm technology node and beyond","authors":"N. Collaert, A. De Keersgieter, A. Dixit, I. Ferain, L. Lai, D. Lenoble, A. Mercha, A. Nackaerts, B. Pawlak, R. Rooyackers, T. Schulz, K.T. Sar, N. Son, M. V. van Dal, P. Verheyen, K. von Arnim, L. Witters, De Meyer, S. Biesemans, M. Jurczak","doi":"10.1109/ESSDERC.2007.4430899","DOIUrl":null,"url":null,"abstract":"Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"66","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC 2007 - 37th European Solid State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2007.4430899","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 66
Abstract
Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.
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