FPGA Implementation of ARM MCU with Five-stage Pipeline

Abstract

We proposed a new 32-bits Microcontroller core with a five-stage pipeline based on the Cortex-M0 microcontroller with the three-stage pipeline of ARM Holdings PLC. The architecture provides flexible banked memory to support the mixed-width instruction set architecture (ISA), which improves the clock rate of Cortex-M0 and reduces the memory size in the ARM MCU. In this study, we implemented the ARM MCU by using Harvard architecture. Thus, the design speeds up the clock rate of processing as the instruction and the data are fetched simultaneously. The design was described in System Verilog HDL, simulated under Modelsim environment, and implemented by Altera DE10 FPGA platform. The results of FPGA implementation showed that the ARM MCU worked normally under 80 MHz in comparison with Cortex-M0 which works under 50MHz. The proposed architecture provides higher throughput and is compatible with the instruction set of Cortex-M0.