A 2.88mm2 50M-intersections/s ray-triangle intersection unit for interactive ray tracing

Abstract

A ray-triangle intersection unit design for ray-tracing in embedded systems is fabricated by TSMC 0.13 mum technology. Bounding volume hierarchy data structure is employed to reduce the on-chip memory requirement. Multi-threading technique is used in the traversal unit to improve the hardware utilization and performance. Moreover, the cost of intersection unit is optimized with folding technique and reconfigurable datapath. Furthermore, the memory bandwidth is reduced with the proposed multi-bank cache architecture. It can provide the processing speed of 50 M-intersections/s with only 2.88 mm2 in hardware cost.