Implications of a new architectural approach to designing ECL megacells

Abstract

One high-performance technology, ECL (emitter-coupled logic), is emerging with an innovative architecture, derived from identified customer needs, which blurs the distinction between current gate arrays and cell-based products. Short of being full custom, the customer definable array (CDA) approach used for the Motorola MCAIV MCA50000ECL gate array benefits large functional units like multipliers, barrel shifters, and ALUs. Some pragmatic aspects of the architecture-silicon relationship are examined for the UDA megacell design technique embracing ECL and BiCMOS on the same chip. The MCAIV ECL CDA impact on chip specifications is examined by describing various tiles-such as 4:1 MUX, latch D-flip-flop with gated inputs and a full adder-used as logic components, and by comparing their implementation on conventional arrays with the compacted CDA; similar tiles also have their place in memory implementations. Like comparisons of higher-level functions (e.g. multipliers, barrel shifters) built from these primitives are explored.<>