A novel 8T SRAM with minimized power and delay

Abstract

In this paper, a novel 8T SRAM cell is proposed which aims at decreasing the delay and lowering the total power consumption of the cell. The threshold voltage variations in the transistor affect the read and write stability of the cell. Also, power dissipation increases with the number of transistors which in turn affects the read and write stability. The proposed 8T SRAM bitcell is designed using 180 nm CMOS, n-well technology with a supply voltage of 1.8 V. The results show that the average delay has been improved by 80 % compared to the conventional 6T cell. The total power is improved by 14.5 % as compared to conventional 6T SRAM cell.