An accurate pipeline model for optimizing retargetable compiler

Abstract

Model-based, retargetable compilers are a popular means of reducing time-to-market for novel processor architectures. In this paper, we present an efficient pipeline model for instruction scheduling in a retargetable compiler. Compared to existing retargetable compilers, this pipeline model: allows for instruction scheduling optimizations even for complex pipelines with multiple functional units, allows for simpler re-targetability for novel architectures and improves by 14% the average compile-time of applications for complex architectures. The applications compiled with our pipeline model show the same performance as compiled with a classic, “hand-written” compiler.