Real-time DRAM throughput guarantees for latency sensitive mixed QoS MPSoCs

Abstract

The trend towards integration is leading to the design of multi- and many-core platforms that accommodate processing tiles (requestors) with different memory requirements. Such platforms require a memory controller capable of providing low-latency best-effort (BE) service for some requestors and guaranteed throughput (GT) for others. Although there are realtime controllers that support the concept of different traffic classes, they do not efficiently handle scenarios with multiple BE and GT requestors. We propose a memory controller that tackles this problem, providing low latency for BE requestors and real-time guarantees for GT ones. We support the guarantees with a formal timing analysis. Our experiments confirm that our approach enforces tight guarantees for GT requestors, while simultaneously reducing the latency of BE ones by up to 67%, when compared with a baseline memory controller.