Efficient Design and FPGA Implementation of Digital Filter for Audio Application

Abstract

Digital Filters are important elements in Digital Signal Processing (DSP). Major factors influencing in the designing an efficient digital filter are computational requirements, memory and finite word length effects. In order to meet these requirements, the order of the digital filter must be kept as small as possible by selecting appropriate filter design method. For Simulating the performance of the digital filter, the filter coefficients are specified with floating point data type but for implementation on Field Programmable Gate Array(FPGA) they must be represented with fixed point data type to minimize cost and power consumption by minimizing the word length. A minimum order Finite Impulse Response (FIR) digital filter is designed for filtering noise from audio signal. It is synthesized using Xilinx ISE9.1 for Spartan 3E-1200 FPGA board using Factored Canonic Signed Digit (FCSD) and Distributed Arithmetic architectures for optimal utilization of FPGA resources.