A power management control scheme for ultra-low power SoCs

Abstract

Because the subthreshold current has an exponential relationship with the supply voltage and the threshold voltage (Vth), it leads to the delay changes exponentially with PVT. To mitigate the impacts caused by PVT variations, increasing the power supply voltage is a simple and effective method. In this paper, a power management control (PMC) scheme for ultra-low power SoCs is proposed. According to the different blocks, different delay detection circuits are inserted into the corresponding critical delay paths. To validate the proposed PMC scheme, a design example for subthreshold SRAM is implemented. The simulation results show that the proposed PMC scheme can mitigate the effects caused by PVT fluctuations upon the subthreshold SRAM circuit effectively at the minimum cost of the power.