{"title":"Simulation study for Dual Material Gate Hetero-Dielectric TFET: Static performance analysis for analog applications","authors":"Upasana, R. Narang, Mridula Gupta, M. Saxena","doi":"10.1109/INDCON.2013.6725867","DOIUrl":null,"url":null,"abstract":"This paper presents simulation study of Static characteristics for DMG (Dual Material Gate) Hetero-Dielectric (H-D) Tunnel FET. Here, two previously reported device architectures i.e. a DMG Single Dielectric TFET and SMG (Single Material Gate) Hetero-Dielectric TFET have been optimized by tuning the work functions and length and later on their combined impact on the proposed device architecture i.e. DMG Hetero-Dielectric Tunnel FET (DMG H-D TFET) is been studied. Electrical parameters such as threshold voltage, drain current I<sub>ds</sub>, Sub threshold Slope, I<sub>on</sub> to I<sub>off</sub> ratio, ambipolar current I<sub>amb</sub> have been studied. Some of the important analog parameters like transconductance g<sub>m</sub>, drain conductance g<sub>d</sub>, Output resistance R<sub>out</sub>, transconductance generation efficiency g<sub>m</sub>/I<sub>ds</sub> have also been studied using ATLAS Device Simulation Software.","PeriodicalId":313185,"journal":{"name":"2013 Annual IEEE India Conference (INDICON)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Annual IEEE India Conference (INDICON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INDCON.2013.6725867","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 21
Abstract
This paper presents simulation study of Static characteristics for DMG (Dual Material Gate) Hetero-Dielectric (H-D) Tunnel FET. Here, two previously reported device architectures i.e. a DMG Single Dielectric TFET and SMG (Single Material Gate) Hetero-Dielectric TFET have been optimized by tuning the work functions and length and later on their combined impact on the proposed device architecture i.e. DMG Hetero-Dielectric Tunnel FET (DMG H-D TFET) is been studied. Electrical parameters such as threshold voltage, drain current Ids, Sub threshold Slope, Ion to Ioff ratio, ambipolar current Iamb have been studied. Some of the important analog parameters like transconductance gm, drain conductance gd, Output resistance Rout, transconductance generation efficiency gm/Ids have also been studied using ATLAS Device Simulation Software.