Multilevel Storage Cell Characterization and Behavior Modeling of a Crossbar Computational Array in ESF3 Flash Technology : (Invited Paper)

Abstract

Analog and mixed signal vector-matrix multipliers (VMMs) in non-volatile memory cells provide a pathway way to energy and area efficient computation that rivals traditional DSP units. The ability to store multiple bits of data in each floating-gate device for a long amount of time allows for ideal use as hardware accelerators for neural networks. However, current implementations of the technology are impeded by large peripheral circuit overhead. In this work, steps towards a fully-realized NVM-based VMM ASIC are taken. In the 55-nm process, a test array of embedded NOR-flash memory (ESF3) from SST was implemented and fabricated. Multi-bit storage has been demonstrated within the 2x2 array via voltage-mode programming. Secondly, behavioral emulation of the VMM is implemented on a Kintex-7 FPGA to prototype the digital periphery, algorithms, and configurations necessary to embed the NVM-based VMM in a system on chip (SoC). Two quadrant kernel processing is demonstrated at a throughput of 1.8 GOPs for a 72x16 array which can process a 128x128 image @ 250 fps.